The processes for fabricating semiconductor devices includes process steps for providing isolation regions that contain dielectric materials that provide the necessary protection for assuring proper function of the formed electronic integrated circuit design. The process includes LOCOS which is localized oxidation of silicon. This process typically begins by depositing a silicon nitride layer over a silicon dioxide layer (barrier oxide) to a thickness in the range of 0.05 .mu.m. to 0.10 .mu.m. The silicon nitride is typically deposited using low-pressure chemical vapor deposition (LPCVD) techniques. A photoresist mask layer, comprising any appropriate commercially available photoresist material known in the industry, is then deposited over the silicon nitride layer The photoresist mask layer is then patterned for forming isolation trenches. Upon etching, the isolation trench regions are formed adjacent silicon oxide layer and the silicon nitride layer and a portion of the photoresist layer. Typically, in order to form the trench regions, the upper surface of the substrate is etched a small amount, approximately 0.25 .mu.m. An oxide layer is formed in the isolation regions by depositing a thick pad of silicon dioxide using tetraethylorthosilicate (TEOS) as the source for deposition of silicon dioxide. The thickness of the oxide pad, also referred to as a field oxide (FOX) pad, is in the range of 1.2 .mu.m to 1.5 .mu.m. The process further includes polishing of the formed isolation pads to a surface level and thickness substantially even with the silicon nitride level. Subsequent to formation of the oxide pads the silicon nitride and silicon dioxide layer regions are removed by wet etching to expose the active region which will be used to form the various integrated circuit components. The wet etching is typically done using hot phosphoric acid to first etch the silicon nitride layer, then by dipping the substrate in a hydrofluoric acid (HF) dip to etch the silicon dioxide layer.
As seen from the foregoing, formation of the trench region, in accordance with prior art techniques, erodes the adjacent barrier oxide and silicon nitride layers protecting the active regions. Thus, a need is seen to exist for a method of forming the isolation trenches without eroding the adjacent silicon nitride pads and barrier oxide that overlay the active regions of the semiconductor structure.
Accordingly, a primary object of the present invention is to provide a method for forming isolation trenches such that the adjacent structure protecting the active semiconductor substrate is not eroded during etching processes used to form the trench regions.